1. Field of the Invention
The present invention relates to a MOS semiconductor device, that is, a semiconductor device having a MOS structure and a method of manufacturing the semiconductor device, and more particularly to an improvement in suppression of a short channel effect of a threshold voltage.
2. Description of the Background Art
First of all, names to be used in this specification will be described. In this specification, a general semiconductor device comprising a structure including a channel region, a pair of source-drain regions interposing the channel region therebetween and a gate electrode opposed to the channel region with an insulating film interposed therebetween, that is, a MOS structure will be hereinafter referred to as a MOS semiconductor device. Typical examples include a MOS transistor, whereas the MOS semiconductor device is not restricted to the MOS transistor. Although a set of a source region and a drain region which interpose a channel region therebetween will be referred to as xe2x80x9ca pair of source-drain regionsxe2x80x9d in this specification, the expression does not always imply that the source region and the drain region have shapes symmetrical with each other.
FIG. 60 is a plan view showing a conventional MOS semiconductor device. FIGS. 61 and 62 are sectional views taken along the lines Kxe2x80x94K and Lxe2x80x94L in FIG. 60, respectively. A device 150 is constituted as a MOS transistor in which a channel region 95, a pair of source-drain regions 98 and 99 interposing the channel region 95 therebetween and an isolating film 92 are selectively formed in a main surface of a semiconductor substrate 91.
The semiconductor substrate 91 is a silicon substrate containing a P-type impurity, and the source-drain regions 98 and 99 contain an N-type impurity. A gate electrode 94 is opposed to an upper surface of the channel region 95 with a gate insulating film 93 interposed therebetween. In other words, the device 150 is constituted as an N-channel type MOS transistor. The gate electrode 94 is formed of polysilicon doped with an N-type impurity.
The gate insulating film 93 is constituted as a silicon oxide film having a thickness of 5 nm, for example. The isolating film 92 is constituted as a silicon oxide film buried in a trench having a depth of approximately 0.3 xcexcm which is formed to surround the channel region 95 and the source-drain regions 98 and 99. More specifically, the isolating film 92 constitutes a trench isolation structure. Consequently, the channel region 95 and the source-drain regions 98 and 99 are isolated from other elements (for example, other channel regions and source-drain regions which are not shown) formed on the main surface of the semiconductor substrate 91.
An upper surface of the isolating film 92 is on a level with upper surfaces of the channel region 95 and the source-drain regions 98 and 99. For this reason, the gate electrode 94 is opposed to only the upper surface of the channel region 95. Accordingly, a direction in which an electric field is to be applied from the gate electrode 94 to the channel region 95 is restricted to a vertical direction with respect to the same upper surface.
In the conventional MOS semiconductor device, as described above, the electric field to be applied from the gate electrode 94 to the channel region 95 is restricted to that in the vertical direction with respect to the upper surface. Therefore, there is a problem in that control capabilities of the gate electrode 94 for the channel region 95 are low. Accordingly, as a gate length is reduced with microfabrication of a device, the influence of a drain field is increased so that a threshold is reduced considerably. Thus, a so-called xe2x80x9cshort channel effectxe2x80x9d is caused.
In FIGS. 61 and 62, a channel depletion layer 95a generated by a gate field and a drain depletion layer 99a generated by a drain field come in contact with each other at a gate-drain end (that is, an end of the channel region 95 which is adjacent to the drain region 99) and a space charge is distributed through so-called xe2x80x9ccharge sharexe2x80x9d. These depletion layers are generated when a gate voltage VG is higher than zero (0 less than VG) and a drain voltage VD is higher than zero (0 less than VD). When the gate length is reduced, a ratio of the drain depletion layer 99a to the channel depletion layer 95a is increased so that a threshold voltage is largely influenced by the drain voltage. Consequently, the threshold voltage is reduced. This implies the short channel effect.
In order to solve the above-mentioned problems of the conventional art, it is an object of the present invention to provide a MOS semiconductor device capable of suppressing a short channel effect of a threshold voltage and a method suitable for manufacturing the MOS semiconductor device.
A first aspect of the present invention is directed to a MOS semiconductor device comprising: a semiconductor layer which has a channel region and a pair of source drain regions interposing the channel region therebetween; an isolating film formed on a surface of the semiconductor layer to surround the channel region and the pair of source drain regions; and a gate electrode formed on side surfaces of the channel region that expose to a trench formed on surface portions of the isolating film adjacent to the channel region and on an upper surface of the channel region with a gate insulating film interposed therebetween, thereby covering the upper surface and the at least a part of the side surfaces in the channel region with the gate insulating film interposed therebetween and setting a gate upper surface step defined by a step between an upper surface of a portion covering the channel region and an upper surface of a portion covering the isolating film to be equal to or smaller than a half of a gate length defined by a width of the portion covering the channel region.
Preferably, the trench is formed in such a depth that almost whole side surfaces of the channel region expose, and the gate electrode covers the almost whole side surfaces of the channel region with the gate insulating film interposed therebetween.
A second aspect of the present invention is directed to the MOS semiconductor device according to the first aspect of the present invention, wherein the isolating film has a first isolating film and a second isolating film which are formed of materials different from each other, the first isolating film is provided between the semiconductor layer and the second isolating film so as to cover a bottom surface and a part of side surface of the second isolating film, and the trench is formed on a surface of the first isolating film to expose the first isolating film on its bottom, to expose the channel region on its first side surfaces and to expose the second isolating film on its second side surfaces facing to the first side surfaces.
A third aspect of the present invention is directed to the MOS semiconductor device according to the first aspect of the present invention, wherein the semiconductor layer is an SOI layer of an SOI substrate having a semiconductor substrate, an insulating layer and the SOI layer that are formed one on another in this order.
A fourth aspect of the present invention is directed to the MOS semiconductor device according to the third aspect of the present invention, wherein the trench is formed in such a depth that the insulating layer exposes, and the gate electrode covers almost whole side surfaces of the channel region with the gate insulating film interposed therebetween.
A fifth aspect of the present invention is directed to the MOS semiconductor device according to the fourth aspect of the present invention, wherein the trench is formed to expose at least a part of a bottom surface of the channel region, and the gate electrode covers the at least a part of the bottom surface of the channel region with the gate insulating film interposed therebetween.
A sixth aspect of the present invention is directed to a MOS semiconductor device comprising: an SOI substrate having a semiconductor substrate, an insulating layer and a semiconductor layer that are formed one on another in this order, the semiconductor layer having a channel region and a pair of source drain regions interposing the channel region, and the channel region being provided with a space between the insulating layer and itself in a part of a bottom surface thereof; and a gate electrode covering a part of a surface of the channel region with the gate insulating film interposed therebetween, the part of the surface of the channel region having contact neither with the pair of source drain regions nor with the insulating layer.
A seventh aspect of the present invention is directed to the MOS semiconductor device according to the first, third or sixth aspect of the present invention, wherein a width of the trench is equal to or smaller than a double of a thickness of the gate electrode.
An eighth aspect of the present invention is directed to the MOS semiconductor device according to the first, third or sixth aspect of the present invention, wherein a channel width of the channel region is set to be equal to or smaller than a double of a maximum channel depletion layer width.
A ninth aspect of the present invention is directed to the MOS semiconductor device according to the first, third or sixth aspect of the present invention, wherein the semiconductor layer is divided into a plurality of unit semiconductor layers arranged in a direction of a channel width with a space therebetween, and a pair of side surfaces and an upper surface of a channel region of each of the unit semiconductor layers are covered by the gate electrode with the insulating film interposed therebetween.
A tenth aspect of the present invention is directed to a method of manufacturing a MOS semiconductor device comprising the steps of (a) preparing a substrate having a semiconductor at least in a portion of a main surface thereof, (b) selectively etching the main surface to cause the main surface to selectively recede, thereby forming a semiconductor layer selectively protruded upward from the main surface which has receded, (c) forming an isolating film on the main surface receding at the step (b) to surround the semiconductor layer leaving a trench to which at least a part of a pair of side surfaces of a partial region of the semiconductor layer are exposed as side walls, (d) forming an insulating film to cover the upper surface and the at least a part of the side surfaces of the partial region after the step (b) or the step (c), (e) after the step (d), forming a conductive material to cover the partial region of the semiconductor layer, the trench and the upper surface of the isolating film thereacross, thereby forming a gate electrode such that the upper surface and the at least a part of the side surfaces of the partial region are covered by the gate electrode with the insulating film interposed therebetween and a gate upper surface step defined by a step between an upper surface of a portion covering the partial region and an upper surface of a portion covering the isolating film is set to be equal to or smaller than a half of a gate length defined by a width covering the partial region, and (f) selectively introducing an impurity by using the gate electrode as a shield to form a pair of source drain regions in a pair of regions in the semiconductor layer with the partial region interposed therebetween, thereby causing the partial region to be a channel region.
An eleventh aspect of the present invention is directed to the method of manufacturing a MOS semiconductor device according to the tenth aspect of the present invention, wherein the conductive material is formed in a thickness which is equal to or larger than a half of a width of the trench at the step (e).
A twelfth aspect of the present invention is directed to the method of manufacturing a MOS semiconductor device according to the tenth or eleventh aspect of the present invention, wherein an SOI substrate having an insulating layer and an SOI layer formed thereon is prepared as the substrate at the step (a).
A thirteenth aspect of the present invention is directed to the method of manufacturing a MOS semiconductor device according to the twelfth aspect of the present invention, wherein the selective etching for causing the main surface to selectively recede is carried out until the insulating layer is exposed in a portion where the semiconductor layer is not protruded at the step (b), and the isolating film is formed at the step (c) such that a bottom surface of the trench reaches the insulating layer, and thereby at the step (e), the gate electrode is formed to cover almost the whole side surfaces in addition to the upper surface of the partial region with the insulating film interposed therebetween.
A fourteenth aspect of the present invention is directed to the method of manufacturing a MOS semiconductor device according to the thirteenth aspect of the present invention, further comprising the step of (g) after the step (c) and before the step (d), selectively forming a cavity to be coupled to the trench in a surface portion of the insulating layer such that at least a part of a bottom surface of the partial region is exposed, the insulating film being formed to cover the at least a part of the bottom surface in addition to the upper and side surfaces of the partial region at the step (d), and the conductive material being formed at the step (e) to fill up the cavity formed at the step (g) so that the gate electrode is formed to cover the at least a part of the bottom surface in addition to the upper and side surfaces of the partial region with the insulating film interposed therebetween.
A fifteenth aspect of the present invention is directed to the method of manufacturing a MOS semiconductor device according to any of the tenth to twelfth aspects of the present invention, wherein the step (c) includes the steps of (c-1) depositing a material of the isolating film on the substrate to cover the semiconductor layer, (c-2) causing an upper surface of the material of the deposited isolating film to recede to approach a level of an upper surface of the semiconductor layer, and (c-3) after the step (c-2), selectively etching the material to cause the upper surface of the material to recede downward. from the upper surface of the semiconductor layer in a portion adjacent to the side surfaces of the partial region, thereby forming the trench.
A sixteenth aspect of the present invention is directed to the method of manufacturing a MOS semiconductor device according to any of the tenth to twelfth aspects of the present invention, wherein the step (c) further includes the steps of (c-1) depositing a first insulating material to cover the receding main surface and the upper and side surfaces of the semiconductor layer in a smaller thickness than a height of the semiconductor layer from the receding main surface, (c-2) depositing a second insulating material different from the first insulating material on the first insulating material, (c-3) causing an upper surface of a composite material including the first and second insulating materials which are deposited to recede to approach a level of the upper surface of the semiconductor layer, and (c-4) after the step (c-3), carrying out selective etching having a higher etching effect for the first insulating material than the second insulating material, thereby causing an upper surface of the first insulating material to recede downward from the upper surface of the semiconductor layer in a portion adjacent to the side surfaces of the partial region, resulting in formation of the trench.
A seventeenth aspect of the present invention is directed to the method of manufacturing a MOS semiconductor device according to any of the tenth to sixteenth aspects of the present invention, wherein, at the step (c), the isolating film is formed such that an upper surface step defined by a step between the upper surface of the semiconductor layer and the upper surface of the isolating film is set to be equal to or smaller than a half of the gate length.
An eighteenth aspect of the present invention is directed to a method of manufacturing a MOS semiconductor device comprising the steps of (a) preparing an SOI substrate having an insulating layer and an SOI layer formed thereon, (b) selectively etching the SOI layer to cause a main surface of the SOI layer to selectively recede until the insulating layer is selectively exposed, thereby forming a semiconductor layer which is selectively protruded upward from the main surface after the receding, (c) selectively forming a cavity in a surface portion of the insulating layer such that a part of a bottom surface of a partial region of the semiconductor layer is exposed, (d) forming an insulating film to cover an upper surface, a pair of side surfaces and the part of the bottom surface in the partial region, (e) after the step (d), forming a conductive material to fill up the cavity and to cover the partial region, thereby forming a gate electrode to cover the upper surface, the side surfaces and the part of the bottom surface in the partial region with the insulating film interposed therebetween, and (f) selectively introducing an impurity by using the gate electrode as a shield, thereby forming a pair of source drain regions in a pair of regions in the semiconductor layer which interpose the partial region therebetween so that the partial region is caused to be a channel region.
A nineteenth aspect of the present invention is directed to the method of manufacturing a MOS semiconductor device according to any of the tenth to eighteenth aspects of the present invention, wherein a width of the partial region corresponding to a channel width of the channel region is set to be equal to or smaller than a double of a maximum channel depletion layer width at the step (b).
A twentieth aspect of the present invention is directed to the method of manufacturing a MOS semiconductor device according to any of the tenth to eighteenth aspects of the present invention, wherein a region to be the partial region at the step (c) is divided into a plurality of unit regions arranged in a direction of a width corresponding to the channel width of the channel region at the step (b), the insulating film is formed to cover at least a part of a pair of side surfaces and an upper surface in each of the unit regions at the step (d), and a conductive material is formed on the insulating film at the step (e) so that the gate electrode is formed to cover the upper surface and the at least a part of the side surfaces in each of the unit regions with the insulating film interposed therebetween.
A twenty-first aspect of the present invention is directed to the method of manufacturing a MOS semiconductor device according to the twentieth aspect of the present invention, wherein the channel width of each of plurality of unit channel regions formed by the plurality of unit regions is set to be equal to or smaller than a double of a maximum channel depletion layer width at the step (b).
A twenty-second aspect of the present invention is directed to a method of manufacturing a MOS semiconductor device comprising the steps of (a) preparing a substrate having a semiconductor at least in a portion of a main surface thereof, (b) selectively etching the main surface to cause the main surface to selectively recede, thereby forming a semiconductor layer selectively protruded upward from the main surface which has receded, (c) forming an isolating film on the main surface receding at the step (b) to surround the semiconductor layer and to cause an upper surface to be on a level with an upper surface of the semiconductor layer, (d) forming a sacrificial layer to cover an upper surface of a partial region of the semiconductor layer and an upper surface portion of the isolating film adjacent thereto, (e) selectively introducing an impurity by using the sacrificial layer as a shield, thereby forming a pair of source drain regions in a pair of regions in the semiconductor layer interposing the partial region therebetween so that the partial region is caused to be a channel region, (f) forming an insulating layer formed of a different material from that of the sacrificial layer to cover a portion which is not covered by the sacrificial layer over the upper surface of the semiconductor layer and the upper surface of the isolating film, (g) carrying out selective etching having a higher etching effect for the sacrificial layer than the insulating layer, thereby removing the sacrificial layer, (h) executing selective etching using the insulating layer as a shield, thereby causing the upper surface portion of the isolating film to recede downward from the upper surface of the semiconductor layer, (i) forming an insulating film to cover an exposed portion of an upper surface and a pair of side surfaces in the channel region of the semiconductor layer, and (j) forming a conductive material on the insulating film, thereby forming a gate electrode to cover the upper surface and at least a part of the side surfaces in the channel region with the insulating film interposed therebetween.
A twenty-third aspect of the present invention is directed to the method of manufacturing a MOS semiconductor device according to the twenty-second aspect of the present invention, wherein a width of a region to be the partial region corresponding to a channel width of the channel region is set to be equal to or smaller than a double of a maximum channel depletion layer width at the step (b).
A twenty-fourth aspect of the present invention is directed to the method of manufacturing a MOS semiconductor device according to the twenty-second or twenty-third aspect of the present invention, wherein an SOI substrate having an insulating layer and an SOI layer formed thereon is prepared as the substrate at the step (a), the selective etching for causing the main surface to selectively recede is carried out until the insulating layer is exposed in a portion where the semiconductor layer is not protruded at the step (b), and the selective etching for causing the upper surface portion of the isolating film to recede downward is carried out until the insulating layer is exposed at the step (h), the manufacturing method further comprising the step of (k) selectively removing a surface portion of the insulating layer such that a bottom surface of the channel region is exposed after the step (h) and before the step (i), the insulating film being formed to cover the bottom surface in addition to the upper surface and the side surfaces in the channel region at the step (i), and the conductive material being formed on the insulating film at the step (j) so that the gate electrode is formed to cover the bottom surface in addition to the upper surface and the side surfaces in the channel region with the insulating film interposed therebetween.
According to the first aspect of the present invention, the side surfaces as well as the upper surface of the channel region are covered by the gate electrode. Therefore, a short channel effect can be suppressed. Moreover, since the isolating film surrounds the semiconductor layer, an electrical isolation between the semiconductor layer and other elements can be implemented. In addition, the step of the upper surface of the gate electrode is limited to an optimal range. In the process for manufacturing the device, therefore, it is possible to relieve the problem of a halation, thereby setting a thinned portion of the gate electrode within such a range as to have no practical problem. Thus, a device having high precision can be implemented.
According to the second aspect of the present invention, the isolating film does not have the second isolating film in the portion provided under the bottom surface of the trench but has the second isolating film in other portions. Therefore, the trench can easily be formed by using selective etching having a larger etching effect for the first isolating film than the second isolating film.
According to the third aspect of the present invention, it is possible to obtain an advantage that a short channel effect can be suppressed for the device using the SOI substrate.
According to the fourth aspect of the present invention, almost the whole side surfaces of the channel region are covered by the gate electrode. Therefore, the short channel effect can be suppressed more considerably.
According to the fifth aspect of the present invention, at least a part of the bottom surface of the channel region is covered by the gate electrode. Therefore, the short channel effect can be suppressed much more considerably.
According to the sixth aspect of the present invention, the bottom surface of the channel region is covered by the gate electrode leaving a part thereof. Therefore, the short channel effect can be suppressed much more considerably. In addition, a part of the bottom surface of the channel region is coupled to the insulating layer. Therefore, a mechanical strength in the process for manufacturing the device can be increased. As a result, manufacturing yield can be enhanced.
According to the seventh aspect of the present invention, the width of the trench is set to be equal to or smaller than a double of the thickness of the gate electrode. Therefore, the problem of a focal depth can be eliminated so that the gate electrode can be provided with high precision. In other words, a device having higher precision can be implemented.
According to the eighth aspect of the present invention, the channel width is set to be equal to or smaller than a double of the maximum channel depletion layer width. Therefore, the short channel effect can be suppressed more effectively.
According to the ninth aspect of the present invention, the semiconductor layer is divided into a plurality of unit semiconductor layers arranged in the direction of the channel width with a space therebetween. The upper surface and the side surfaces in the channel region of each of the unit semiconductor layers are covered by the gate electrode with the insulating film interposed therebetween. Therefore, the short channel effect can be suppressed and a current capacity can be increased without an enlargement in an area as compared with a conventional device.
According to the tenth aspect of the present invention, at least a part of the side surfaces as well as the upper surface of the channel region are covered by the gate electrode. Therefore, it is possible to obtain a MOS semiconductor device in which the short channel effect can be suppressed. Moreover, the isolating film is formed to surround the semiconductor layer. Therefore, an electric isolation between the semiconductor layer and other elements can be implemented. In addition, the step of the upper surface of the gate electrode is limited to an optimal range. Therefore, it is possible to relieve the problem of a halation, thereby setting the thinned portion of the gate electrode within such a range as to have no practical problem. Furthermore, the impurity is selectively introduced by using the gate electrode as the shield. Consequently, a pair of source drain regions can be formed in self-alignment.
According to the eleventh aspect of the present invention, the width of the trench is set to be equal to or smaller than a double of the thickness of the gate electrode. Therefore, the problem of a focal depth can be relieved so that the gate electrode can be provided with higher precision.
According to the twelfth aspect of the present invention, a device having an advantage that the short channel effect can be suppressed can be fabricated in the SOI substrate.
According to the thirteenth aspect of the present invention, almost the whole side surfaces of the channel region are covered by the gate electrode. Therefore, it is possible to obtain a device in which the short channel effect can be suppressed more remarkably.
According to the fourteenth aspect of the present invention, at least a part of the bottom surface of the channel region is covered by the gate electrode. Therefore, it is possible to obtain a device in which the short channel effect can be suppressed much more remarkably.
According to the fifteenth aspect of the present invention, the isolating film is subjected to the selective etching so that the trench is formed. Therefore, the trench can be formed easily.
According to the sixteenth aspect of the present invention, the upper surface of the first insulating material is caused to recede by using the selective etching having a larger etching effect for the first insulating material than the second insulating material. Thus, the upper surface of the isolating film is caused to recede in the portion adjacent to the channel region. Consequently, the receding surface of the isolating film in which the gate electrode is buried is formed in self-alignment without using a mask pattern which needs alignment.
According to the seventeenth aspect of the present invention, the step between the height of the upper surface of the isolating film and that of the upper surface of the semiconductor layer is limited to the optimal range. Therefore, it is possible to relieve the problem of a halation, thereby setting the thinned portion of the gate electrode within such a range as to have no practical problem without adding a special step to the step of forming the gate electrode.
According to the eighteenth aspect of the present invention, a part of the bottom surface of the channel region is covered by the gate electrode. Therefore, it is possible to obtain a device in which the short channel effect can be suppressed much more remarkably. In addition, the cavity is formed such that a portion to be coupled to the insulating layer remains on the bottom surface of the channel region. Therefore, a mechanical strength can be increased. As a result, manufacturing yield can be enhanced.
According to the nineteenth aspect of the present invention, the channel width is set to be equal to or smaller than a double of the maximum channel depletion layer width. Therefore, it is possible to obtain a device in which the short channel effect can be suppressed more effectively.
According to the twentieth aspect of the present invention, the channel region is divided into a plurality of unit channel regions arranged in the direction of the channel width. The upper surface and at least a part of the side surfaces in each of the unit channel regions are covered by the gate electrode with the insulating film interposed therebetween. Therefore, it is possible to obtain a device in which the short channel effect can be suppressed and a current capacity can be increased without an enlargement in an area as compared with a conventional device.
According to the twenty-first aspect of the present invention, the channel width of each of the unit channel regions is set to be equal to or smaller than a double of the maximum channel depletion layer width. Therefore, it is possible to obtain a device in which the short channel effect can be suppressed more effectively.
According to the twenty-second aspect of the present invention, by using the insulating layer as a shield which is formed as a mold through the Damascene method, the upper surface of the isolating film is caused to recede in the portion adjacent to the channel region. Consequently, the receding surface of the isolating film in which the gate electrode is buried is formed in self-alignment without using a mask pattern which needs alignment.
According to the twenty-third aspect of the present invention, the channel width is set to be equal to or smaller than a double of the maximum channel depletion layer width. Therefore, it is possible to obtain a device in which the short channel effect can be suppressed more effectively.
According to the twenty-fourth aspect of the present invention, the channel region is formed to float above the receding main surface of the substrate and the gate electrode is formed to cover the upper surface, the pair of side surfaces and the bottom surface in the channel region with the insulating film interposed therebetween. Therefore, it is possible to obtain a device in which the short channel effect can be suppressed more remarkably.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.